The present invention relates to a semiconductor device, and to, for example, a technology effective when applied to a semiconductor device in which a plurality of semiconductor components such as semiconductor chips are electrically coupled to each other through an interposer.
There has been described in each of Japanese Unexamined Patent Application Publication No. 2010-538358 (Patent Document 1), Japanese Unexamined Patent Publication Laid-Open No. 2013-138177 (Patent Document 2), Japanese Unexamined Patent Publication Laid-Open No. 2014-11169 (Patent Document 3), U.S. Pat. No. 8,653,676 (Patent Document 4), and Japanese Unexamined Patent Publication Laid-Open No. 2014-11284 (Patent Document 5), a semiconductor device in which a plurality of semiconductor chips are electrically coupled to each other via an interposer.
Further, there has been described in Japanese Unexamined Patent Publication Laid-Open No. 2008-153542 (Patent Document 6), a multilayer wiring substrate in which signal wirings and ground wirings are alternately provided.